Yield Enhancement Designs for Wsi Cube Connected Cycles

In this paper, we present and analyze yield enhancement designs for wafer scale Cube Connected Cycles (CCC). Improvements in yield can be achieved through silicon area reduction and/or through the incorporation of defect/fault tolerance into the architecture. Consequently, we first propose a new compact layout strategy for CCC. We then present a novel implementation of wafer scale CCC based on a universal building block. This implementation facilitates the introduction of redundancy to achieve defect-tolerance. Finally, we derive expressions for the yield of various yield enhancement designs and compare them numerically for several sizes of wafer scale ccc.